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Semiconductors

IB Labs’ technology tailors to ever shrinking device sizes in the semiconductor industry, in respect to metrology and failure analysis of devices. An innovator in the in-situ surface preparation for electrical and physical failure analysis, IB Labs’ offers advanced integrated ion-milling and imaging solutions.

Typical applications include front-side planar delayering, back-side thinning, ultra-shallow sputtering for elemental and molecular depth profiling and STEM metrology

Front-side planar polishing and delayering:

Usage Benefits
Metal-to-Metal delayering with real-time control and end-point detection over wide variable treatment areas from ~10µm to mm ~10x faster than currently used manual polishing
Search for metal bridging Planarity, depth control, automation superior to manual polisher or BIM
Sample preparation for probing at the metal or contact level Surface roughness superior to FIB
2D-to-3D reconstruction when combined with imaging Multiple treatment sites within a die
Reverse engineering  

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Back-side thinning:

Usage Benefits
Sample preparation for Photoemission (PEM) and Laser Voltage Microscopy (LVx) at the chip or board level Minimal impact on a chip thermal and electrical integrity due to site-specific, non-contact milling
  Variable size, single or multiple treatment areas within a chip

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Surface sputtering for depth profiling:

Usage Benefits
Ultra shallow depth profiling for SIMS, AES and XPS, Raman applications Superior planarity and roughness of a sputter crater compared to state of the art depth-profiling instruments
  Enables unique combination of high-resolution depth profiling and imaging

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STEM Metrology:

Usage Benefits
Unique site-specific STEM preparation at the wafer level STEM sampling and analysis by using both front- and back-side thinning within a chip or wafer without lifting out a specimen
No limitations of lift-out sample size and observation area in a STEM mode as compared to other techniques Enables CD-STEM wafer metrology and defect review

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